Reverse Engineering Transmission Sensor PC Board

Reverse Engineering Transmission Sensor PC Board

Reverse Engineering Transmission Sensor PC Board will start to a physical sample, before we can fully extract its layout it is necessary to know the way out component routing and placing, methods to estimate the length of a specific net include: heuristically computing a Steiner tree between the terminals, computing a minimum spanning tree between the terminals, building a chain through the terminals, or taking half the length of the perimeter of the bounding box enclosing all the terminals of the net.

Keep in mind, that for nets with two terminals and using Manhattan distances (a typical metric in PCB and VLSI design) all these measures give the same result. A survey on placement methods and substitute objectives can be found in Preas and Karger (1986).

Another possible objective during placement is to minimize the number of wire crossings. According to Stallmann et al. (2001) this can be modeled as a bigraph crossing problem in the following way: Let  G = (V, E) be a bipartite graph with partitions V₁ and V₂ and let G be embedded in the plane so that the nodes in V_i occupy distinct positions on the line y = i and the edges are straight lines.

For an embedding f (G) of G in the plane, the crossing number C _f (G) is the number of line intersections induced by f . This number depends only on the permutation of V_i along y = i and not on specific x-coordinates. The bigraph crossing number C(G) is defined as C(G) = min _f C_f (G). The computation of C(G) is NP-hard (Garey and Johnson, 1979). Some heuristics for crossing minimization are presented and compared in Stallmann et al. (2001).