Reverse Engineering Multilayer PCB Layout to Confirm Power Supply Layer Design

Reverse Engineering Multilayer PCB Layout needs to confirm multilayer power supply sources reference plane: multilayer PCB power supply layer will be cut off into physical areas with different voltages and this point can be modified by clone PCB board, designate the eleventh layer as multilayer power supply layer, then its adjacent layers include tenth layers and bottom layer will encounter unexpected revert route for signal current and make the aperture on the revert route.

As for the high speed signal, this kind of unreasonable revert route design will bring severe security issue. As a result of that, high speed PCB board reverse engineering and layout should keep sufficient distance from power supply reference plane.

Multiple copper clad layer can effective decrease the impedance in the PCB and reduce the common mode electro-magnetic interference;

Signal layer should held close decoupling with adjacent reference plane and layers which means the inter-media thickness among the signal layers and adjacent copper layer should be keep as small as possible, and power supply copper clad should be close to ground copper clad as much as it can, as for this point,  printed circuit board layout optimization can realize it.

PCB layout combination rationally: in order to complete the complicate layout on the PCB, it is inevitable to put the layer to layer switch into practice, and make the two layers cross by one signal route as layout PCB combination.

Switch among layers need to ensure the revert current can flow back from one reference plane to another. As a matter of fact, the best PCB reverse engineering layout combination is avoiding the revert current flow from one reference plane to another, from 3^rd layer to 5^th layer, from 5^th layer to 7^th layer, and then from 7^th to 9^th can be viewed as a layout combination.

But regards 3^rd layer and 9^th layer as a combination is not a reasonable option. Since it need to revert the current from 4^th layer to decoupling 6^th layer, and then from 6^th layer to 8^th layer which is not a smooth route for a revert current. Although can place the decoupling capacitor on around the through hole or decrease the medium thickness among the reference layer to reduce the ground bouncing.

Design the layout orientation: in the same signal layer, ensure most of the layout orientation will be the same, at the same time make cross intersection with adjacent signal layer of PCB reverse engineering.

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