FPGA Lead Improvement on PCB Board Cloning

The improvement of FPGA lead hasn’t completed, designer has already reported the information to the supervisor who in charge of the monitoring of PCB Board Cloning, due to the progress reason, designer will normally launch the progress of Cloning before the pinout system of FPGA has been optimized.

Under the circumstance that all of the pinout system has been clarified, Engineer start to make plan for the FPGA system, and designer will take the other component’s lead to FPGA into account after the completion of plan. And originally the IO will be planned on the right side of FPGA, but now it will locate in the left side of the FPGA, and it will directly lead to the completely alternation of lead output and preliminary plan.

Due to the higher level optical job on the side of designer, they can adapt to these changes through the deletion the wires on the outskirt of FPGA around, to replace the modification of topology route.

However, the element being affected will not only FPGA, these new leads output will affect other related components’ lead. In order to adapt to entry route of flat package lead, these routes terminals will need to move too; otherwise these leads will have twisted and waste the precious layout space;

Regarding to these bytes twisting requires to save more space for the wires and through hole, in the final stage of PCB Board cloning maybe unable to be satisfied. And if the progress is too tense, probably these wires will need to make some adjustment. The critical point is topology plan provides a higher resolution for the whole project and makes the ECO became much easier.