Engine Timing System Printed Circuit Board Reverse Engineering

Engine Timing System Printed Circuit Board Reverse Engineering

Continuing advances in Engine Timing System Printed Circuit Board Reverse Engineering techniques increase the requirements on physical layout algorithms. From a theoretical point of view it would be obviously best to use a holistic approach to find a physical Printed Circuit Board design. It is clear that this is far from reality in practice.

While some subproblems such as via minimization and layer assignment tend to be reintegrated with routing, new subproblems like pin assignment for the IC packages emerge.

For research, one of the biggest shortcomings is the absence of publicly available benchmark cases. Readers with more than superficial interest in the subject presented here may have wished to obtain a sound and fact based judgment of the relative merits and disadvantages of the various approaches to placement and routing surveyed in this paper.

We would love to present such findings, but for many reasons it is impossible to make fair test runs necessary for such comparisons. Clearly, every group of authors shows in their papers that their approach has some advantages in comparison to other methods on the examples considered. But it is not possible to obtain the codes and the test instances to make “neutral” runs.

 

Moreover, production codes are usually fine tuned to specific customer demands, particular layout properties, and design rules to which competititors (usually) do not get access. In this sense no two routing or no two placement programs address exactly the same problem.

This deficiency could be remediated if the PCB/VLSI layout community would have access to a large collection of real instances, including all specific layout requirements, allowing to test new codes and ideas in an open competitive environment.

Unfortunately, the electronic industry does not seem to be ready to make up-to-date realistic test instances publicly available and thus, “benchmarking suites” consist only of small academic (made-up) examples with questionable bearing on real layout problems.

This situation not only makes it difficult to test new ideas, especially for people without access to tool suites, it also makes it difficult to measure advancement in the field. While finding an optimal solution for a contemporary PCB layout problem might be completely out of reach, it could be possible to solve the problems from 20 years ago to optimality. This might give an interesting insight in how much is lost by the standard approach of partitioning the problem into several hierarchically executed steps.