Reverse Engineering 2 Layer PCB Board Layout Parasitic Elements

Reverse Engineering 2 Layer PCB Board Layout Parasitic Elements may cause problem in: parasitic capacitance and parasitic inductance.

When cloning double side PCB Board layout and gerber file, placing two traces close to each other will generate parasitic capacitance.

You can do this: place one trace on top of the other on two different layers; or place one trace beside the other on the same layer,

As shown in below Figure. In these two trace configurations, the change in voltage over time (dV/dt) on one trace may cause current on the other trace.

If the other trace is high impedance, the current generated by the electric field will be converted into voltage.

Fast voltage transients most often occur on the digital side of the analog signal design. If the trace with fast voltage transients is close to the high impedance analog trace, this error will seriously affect the accuracy of the analog circuit after reverse engineering.

In this environment, analog circuits have two disadvantages: their noise tolerance is much lower than digital circuits; high impedance traces are more common