PCB Static Guarding Techniques

PCB Static Guarding Techniques become slightly more complicated when using guarding techniques with the SOIC surface mount (“R”) package, as the 0.05″ pin spacing doesn’t easily allow routing of PCB traces between the pins. But, there is still an effective guarding answer, at least for the inverting case. Figure belows shows guards for the ADI “R” style SOIC package.

Note that for many single op amp devices in this SOIC “R” package, Pins 1, 5, and 8 are “no connect” pins. Historically these pins were used for offset adjustment and/or frequency compensation. These functions rarely are used in modern op amps.

For such instances, this means that these empty locations can be employed in the layout to route guard traces. In the case of the inverting mode (left), the guarding is still completely effective, with the dummy Pin 1 and Pin 3 serving as the grounded guard trace.

This is a fully effective guard without compromise. Also, with SOIC op amps, much of the circuitry around the device will not use through hole components. So, the guard ring may only be necessary on the op amp PCB side.

In the case of the follower stage (right), the guard trace must be routed around the negative supply at Pin 4, and thus Pin 4 to Pin 3 leakage isn’t fully guarded. For this reason, a precision high impedance follower stage using an SOIC package op amp isn’t generally recommended, as guarding isn’t possible for dual supply connected devices.

However, an exception to this caveat does apply to the use of a single-supply op amp as a noninverting stage. For example, if the AD8551 is used, Pin 4 becomes ground, and some degree of intrinsic guarding is then established by default.