Reverse Engineering PWB Against ESD

Reverse Engineering PWB

Reverse engineering PWB need to take the ESD negative effect into consideration, ESD from human body, environment as well as electronic device itself will bring damage to the semiconductor and microcontroller such as penetrate the thin isolation layer in the internal part of electronic components; damage the grid in the MOSFET & CMOS; lock the trigger in the cmos components; melt down the soldering or aluminum wire inside the active device. In order to eliminate the interference and damage generated from ESD device when reverse engineering PWB, multiple measures must be taken:

In the course of PWB reverse engineering, PWB can be designed to against ESD through delayer, approprieate reverse engineering and installation. In the circuit board reverse engineering process, most of the reverse engineering modification can be limited within the add or minus component through prediction. we can prevent the ESD in better way, please view below normal measures:

1. use multilayer PWB as much as you can, as for double side PWB, grounding and power supply layer, and signal layer; grounding track with short distance can effectively reduce the common mode resistance and sensible coupling, make it reach 1/10 or even 1/100 double side PWB. Ensure all the signal layer can attack to a power supply layer or grounding layer. Internal layer track can be taken into account for those PWB with top and bottom assembled with components;

2. as for double side PCB reverse engineering, tight cross grid of power and grounding must be applied. Power supply track attach to grounding wire, connect as much as possible in the vertical and integrate track or filled area. Grid size from one side must lower or equal to 60mm, if possible, should lower than 13mm;

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