PCB Reverse Engineering Topology Plan

Engineer can use IP and furthermore, the application of topology plan and layout tools to support the IP, consequently finish the whole PCB reverse engineering process.
Engineer’s responsibility is through layout as few necessary components as possible, and make critical interconnecting route among these parts to obtain the IP. Once these IP has been obtained, these information will be supplied through engineer and they finish the rest of the work.

Nowadays, it is not anymore necessity to acquire the right design purpose through interconnection and mutual communication. Since the designer can have these information in a very precise way, and provide a tremendous help to them. In most of the PCB reverse engineering process, schematic diagram designer and PCB layout engineer must execute interconnect layout and arrangement, which will consume great amount of both side’s precious time. From the previous experience we can see the interconnect operation is very necessary but too much time consuming and the efficiency is very low.

The preliminary plan provided by the designer could probably be a hand craft drawing, without any proper components with right proportion, bus line width or pin output tips. Accompany with introduction of the layout, although the application of topology technique can acquire some of the components layout and interconnection. This design will probably require to layout more components, acquire other INPUT/OUTPUT and other databus structure and all interconnection to achieve the task.